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cy23ep05 2.5 v or 3.3 v,10-220-mhz, low jitter, 5 output zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07759 rev. *c revised june 7, 2011 features 10 mhz to 220 mhz maximum operating range zero input-output propagation delay, adjustable by loading on clkout pin multiple low-skew outputs ? 30 ps typical output-output skew ? one input drives five outputs 22 ps typical cycle-to-cycle jitter 13 ps typical period jitter standard and high drive strength options available in space-saving 150-mil soic package 3.3 v or 2.5 v operation industrial temperature available functional description the cy23ep05 is a 2.5 v or 3.3 v zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin soic package. it accepts one reference input, and drives out five low-skew clocks. the ?1h version operates up to 220 (200) mhz frequencies at 3.3 v (2.5 v), and has a higher drive strength than the ?1 devices. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the cy23ep05 pll enters a power-down mode when there are no rising edges on the ref input (< ~2 mhz). in this state, the outputs are three-stated and the pll is turned off, resulting in less than 25 a of current draw. the cy23ep05 is available in different configurations, as shown in the ordering information table. the cy23ep05-1 is the base part. the cy23ep05-1h is the hi gh-drive version of the ?1, and its rise and fall times are much faster than the ?1. these parts are not intended for 5 v input-tolerant applications. logic block diagram pll ref clk1 clk2 clk3 clk4 clkout [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 2 of 15 contents pin configuration ............................................................. 3 pin description ................................................................. 3 zero delay and skew control .......................................... 3 absolute maximum conditions ....................................... 4 operating conditions ....................................................... 4 3.3-v dc electrical specifications .................................. 4 2.5-v dc electrical specifications .................................. 5 3.3-v and 2.5-v ac electrical specifications ................. 5 switching waveforms ...................................................... 6 test circuits ...................................................................... 7 supplemental parametric information ............................ 8 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 3 of 15 pin configuration zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between the input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. the output driving the clkout pin will be driving a total load of 5 pf plus any additional load externally connected to this pin. for applications requiring zero input -output delay, the total load on each output pin (including clkout) must be the same. if input-output delay adjustments are required, the clkout load may be changed to vary the delay between the ref input and remaining outputs. for zero output-output skew, be sure to load all outputs equally. for further information refer to the application note titled ?cy2305 and cy2309 as pci and sdram buffers?. 1 2 3 4 5 8 7 6 ref clk2 clk1 gnd v dd clkout clk4 clk3 top view pin description pin signal description 1ref [1] input reference frequency 2clk2 [2] buffered clock output 3clk1 [2] buffered clock output 4 gnd ground 5clk3 [2] buffered clock output 6v dd 3.3 v or 2.5 v supply 7clk4 [2] buffered clock output 8 clkout [2,3] buffered clock output, internal feedback on this pin notes 1. weak pull-down. 2. weak pull-down on all outputs. 3. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew be tween the reference and output. [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 4 of 15 absolute maximum conditions exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. supply voltage to ground potential .................?0.5 v to 4.6 v dc input volta ge ......................................v ss ? 0.5 v to 4.6 v storage temperature................................... ?65 c to 150 c junction temperature.................................................. 150 c static discharge voltage (per mil-std-883, method 3015... .............. ............ > 2000 v notes 4. applies to test circuit #1. 5. applies to both ref clock and internal feedback path on clkout. 6. theta ja, eia jedec 51 test board conditions, 2s2p; theta jc mil-spec 883e method 1012.1. operating conditions parameter description min typ max unit v dd3.3 3.3 v supply voltage 3.0 3.3 3.6 v v dd2.5 2.5 v supply voltage 2.3 2.5 2.7 v t a operating temperature (ambient temperature) ? commercial 0 ? 70 c operating temperature (ambient te mperature) ? industrial ?40 ? 85 c c l [4] load capacitance, < 100 mhz, 3.3 v ? ? 30 pf load capacitance, < 100 mhz, 2.5 v with high drive ? ? 30 pf load capacitance, < 133.3 mhz, 3.3 v ? ? 22 pf load capacitance, < 133.3 mhz, 2.5 v with high drive ? ? 22 pf load capacitance, < 133.3 mhz, 2.5 v with standard drive ? ? 15 pf load capacitance, > 133.3 mhz, 3.3 v ? ? 15 pf load capacitance, > 133.3 mhz, 2.5 v with high drive ? ? 15 pf c in input capacitance [5] ??5pf bw closed-loop bandwidth, 3.3 v ? 1?1.5 ? mhz closed-loop bandwidth, 2.5 v ? 0.8 ? mhz r out output impedance, 3.3 v high drive ? 29 ? output impedance, 3.3 v standard drive ? 41 ? output impedance, 2.5 v high drive ? 37 ? output impedance, 2.5 v standard drive ? 41 ? t pu power-up time for all v dds to reach minimum specified voltage (power ramps must be monotonic) 0.01 ? 50 ms theta j a [6] dissipation, junction to ambient, 8-pin soic ? 131 ? c/w theta j c [6] dissipation, junction to case, 8-pin soic ? 81 ? c/w 3.3-v dc electrical specifications parameter description test conditions min typ max unit v dd supply voltage 3.0 3.3 3.6 v v il input low voltage ? ? 0.8 v v ih input high voltage 2.0 ? v dd + 0.3 v i il input leakage current 0 < v in < v il ?10 ? 10 a i ih input high current v in = v dd ? ? 100 a v ol output low voltage i ol = 8 ma (standard drive) i ol = 12 ma (high drive) ? ? ?0.4 0.4 v v v oh output high voltage i oh = ?8 ma (standard drive) i oh = ?12 ma (high drive) 2.4 2.4 ?? ? v v i dd (pd mode) power down supply current ref = 0 mhz (commercial) ? ? 12 a ref = 0 mhz (industrial) ? ? 25 a i dd supply current unloaded outputs, 66-mhz ref ? ? 30 ma [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 5 of 15 notes 7. for the given maximum loading conditions. see c l in operating conditions table. 8. parameter is guaranteed by design and characterization. not 100% tested in production. 2.5-v dc electrical specifications parameter description test conditions min typ max unit v dd supply voltage 2.3 2.5 2.7 v v il input low voltage ? ? 0.7 v v ih input high voltage 1.7 ? v dd + 0.3 v i il input leakage current 0 < v in < v dd ?10 ? 10 a i ih input high current v in = v dd ? ? 100 a v ol output low voltage i ol = 8 ma (standard drive) i ol = 12 ma (high drive) ? ? ?0.5 0.5 v v v oh output high voltage i oh = ?8 ma (standard drive) i oh = ?12 ma (high drive) v dd ? 0.6 v dd ? 0.6 ?? ? v v i dd (pd mode) power down supply current ref = 0 mhz (commercial) ? ? 12 a ref = 0 mhz (industrial) ? ? 25 a i dd supply current unloaded outputs, 66-mhz ref ? ? 45 ma 3.3-v and 2.5-v ac el ectrical specifications parameter description test conditions min typ max unit 1/t 1 maximum frequency [7] (input/output) 3.3 v high drive 10 ? 220 mhz 3.3 v standard drive 10 ? 167 mhz 2.5 v high drive 10 ? 200 mhz 2.5 v standard drive 10 ? 133 mhz t idc input duty cycle < 133.3 mhz 25 ? 75 % > 133.3 mhz 40 ? 60 % t 2 t 1 output duty cycle [8] < 133.3 mhz 47 ? 53 % > 133.3 mhz 45 ? 55 % t 3, t 4 rise, fall time (3.3 v) [8] std drive, cl = 30 pf, < 100 mhz ? ? 1.6 ns std drive, cl = 22 pf, < 133.3 mhz ? ? 1.6 ns std drive, cl = 15 pf, < 167 mhz ? ? 0.6 ns high drive, cl = 30 pf, < 100 mhz ? ? 1.2 ns high drive, cl = 22 pf, < 133.3 mhz ? ? 1.2 ns high drive, cl = 15 pf, > 133.3 mhz ? ? 0.5 ns t 3, t 4 rise, fall time (2.5 v) [8] std drive, cl = 15 pf, < 133.33 mhz ? ? 1.5 ns high drive, cl = 30 pf, < 100 mhz ? ? 2.1 ns high drive, cl = 22 pf, < 133.3 mhz ? ? 1.3 ns high drive, cl = 15 pf, > 133.3 mhz ? ? 1.2 ns t 5 output to output skew [8] all outputs equally loaded ? 30 100 ps t 6 delay, ref rising edge to clkout rising edge [8] pll enabled at 3.3 v ?100 ? 100 ps pll enabled at 2.5 v ?200 ? 200 ps t 7 part to part skew [8] measured at v dd /2. any output to any output, 3.3 v supply ?150 ? 150 ps measured at v dd /2. any output to any output, 2.5 v supply ?300 ? 300 ps [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 6 of 15 t lock pll lock time [8] stable power supply, valid clocks presented on ref and clkout pins ??1.0ms t jcc [8,9] cycle-to-cycle jitter, peak 3.3 v supply, > 66 mhz, < 15 pf ? 22 55 ps 3.3 v supply, > 66 mhz, < 30 pf, standard drive ? 45 125 ps 3.3 v supply, > 66 mhz, < 30 pf, high drive ? 45 100 ps 2.5 v supply, > 66 mhz, < 15 pf, standard drive ? 40 100 ps 2.5 v supply, > 66 mhz, < 15 pf, high drive ? 35 80 ps 2.5 v supply, > 66 mhz, < 30 pf, high drive ? 52 125 ps t per [8,9] period jitter, peak 3.3 v supply, 66?100 mhz, < 15 pf ? 18 60 ps 3.3 v supply, > 100 mhz, < 15 pf ? 13 35 ps 3.3 v supply, > 66 mhz, < 30 pf, standard drive ? 28 75 ps 3.3 v supply, > 66 mhz, < 30 pf, high drive ? 26 70 ps 2.5 v supply, > 66 mhz, < 15 pf, standard drive ? 25 60 ps 2.5 v supply, 66?100 mhz, < 15 pf, high drive ? 22 60 ps 2.5 v supply, > 100 mhz, < 15 pf, high drive ? 19 45 ps 3.3-v and 2.5-v ac el ectrical specifications (continued) parameter description test conditions min typ max unit note 9. typical jitter is measured at 3.3 v or 2.5 v, 29c, with all outputs driven into the maximum specified load. further informat ion regarding jitter specifications may be found in the application notes, ?understanding data sheet jitter specifications for cypress products.? switching waveforms figure 1. duty cycle timing figure 2. all outputs rise/fall time figure 3. output-output skew t 1 t 2 v dd /2 v dd /2 v dd /2 output t 3 3.3 v(2.5 v) 0 v 0.8 v(0.6 v) 2.0 v(1.8 v) 2.0 v(1.8 v) 0.8 v(0.6 v) t 4 t 5 output output v dd /2 v dd /2 [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 7 of 15 figure 4. input-output propagation delay figure 5. part-part skew switching waveforms (continued) v dd /2 t 6 input clkout v dd /2 v dd /2 v dd /2 t 7 any output, part 1 or 2 any output, part 1 or 2 test circuits 0.1 f v dd 0.1 f v dd clk c load outputs gnd gnd test circuit # 1 [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 8 of 15 supplemental parametric information figure 6. 2.5 v typical room temperature grap h for ref input to clkn delay versus loading difference between clkout and clkn. data is shown for 66 mhz. delay is a weak function of frequency figure 7. 3.3 v typical room temperature grap h for ref input to clkn delay versus loading difference between clkout and clkn. data is shown for 66 mhz. delay is a weak function of frequency -1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500 -20 -10 0 10 20 load clkout- load clkn (pf) delay ref input to clkn (ps) 2.5v standard drive 2.5v high drive -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -20 -10 0 10 20 load clkout- load clkn (pf) delay ref input to clkn (ps) 3.3v standard drive 3.3v high drive [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 9 of 15 figure 8. 2.7 v measured supply current versus frequency, drive strength, loading, and temperature. note that the 30-pf data above 100 mhz is beyond the data sheet specification of 22 pf figure 9. 3.6 v measured supply current versus frequency, drive strength, loading, and temperature. note that the 30-pf high-drive data above 100 mhz is beyond the data sheet specification of 22 pf 0 10 20 30 40 50 60 70 33 66 100 133 166 200 frequency (mhz) 15pf, -45c, standard drive 15pf, 90c, standard drive 15pf, -45c, high drive 15pf, 90c, high drive 30pf, -45c, high drive 30pf, 90c, high drive 0 20 40 60 80 100 33 66 100 133 166 200 233 frequency (mhz) 15pf, -45c, standard drive 15pf, 90c, standard drive 30pf, -45c, standard drive 30pf, 90c, standard drive 15pf, -45c, high drive 15pf, 90c, high drive 30pf, -45c, high drive 30 p f, 90c, hi g h drive [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 10 of 15 figure 10. typical 3.3 v measured cycle-to-cycle jitter at 29 c, versus frequency, drive strength, and loading figure 11. typical 2.5 v measured c ycle-to-cycle jitter at 29 c, versus frequency, drive strength, and loading figure 12. typical 3.3 v measured period jitter at 29 c, versus frequency, drive strength, and loading figure 13. typical 2.5 v measured period jitter at 29 c, versus frequency, drive strength, and loading 0 50 100 150 200 250 300 350 0 50 100 150 200 250 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, standard drive 30 pf, hi g h drive 0 50 100 150 200 250 300 350 400 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, high drive 0 50 100 150 200 250 0 50 100 150 200 25 0 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 pf, standard drive 30 pf, hi g h drive 0 50 100 150 200 250 0 20 40 60 80 100 120 140 160 180 200 frequency (mhz) 15 pf, standard drive 15 pf, high drive 30 p f, hi g h drive [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 11 of 15 figure 14. 100 mhz (top) and 156.25 mhz (bottom) typical phase-noise data versus v dd and drive strength [10] -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 100 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 156.25 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 100 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 100 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 156.25 mhz -140 -130 -120 -110 -100 -90 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 3.3v high drive 3.3v standard drive 2.5v high drive 2.5v standard drive 156.25 mhz note 10. typical jitter is measured at 3.3 v or 2.5 v, 29c, with a ll outputs driven into the maximum specified load. further informa tion regarding jitter specifications may be found in the application notes, ?understanding data sheet jitter specifications for cypress products.? [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 12 of 15 ordering code definitions ordering information ordering code package type operating range pb-free cy23ep05sxc-1 8-pin 150-mil soic commercial cy23ep05sxc-1t 8-pin 150-mil soic ? tape and reel commercial cy23ep05sxi-1 8-pin 150-mil soic industrial CY23EP05SXI-1T 8-pin 150-mil soic ? tape and reel industrial cy23ep05sxc-1h 8-pin 150-mil soic commercial cy23ep05sxc-1ht 8-pin 150-mil soic ? tape and reel commercial cy23ep05sxi-1h 8-pin 150-mil soic industrial cy23ep05sxi-1ht 8-pin 150-mil soic ? tape and reel industrial cy 23ep05 sx (c, i) -1h t tape and reel high output drive strength option temperature range: c = commercial, i = industrial 8-pin soic package pb-free base part number (enhanced performance 5 output zero delay buffer) company code: cy = cypress [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 13 of 15 package drawing and dimensions figure 15. 8-pin (150-mil) soic s8 acronyms document conventions units of measure 51-85066 *d table 1. acronyms used in this document acronym description ac alternating current dc direct current pci peripheral component interconnect pll phase-locked loop sdram synchronous dynamic random access memory soic small-outline integrated circuit table 2. units of measure symbol unit of measure dbc decibels relative to carrier c degree celsius hz hertz mhz megahertz a microampere ma milliampere wohm pf picofarad ps picosecond vvolt wwatt [+] feedback
cy23ep05 document #: 38-07759 rev. *c page 14 of 15 document history page document title: cy23ep05 2.5 v or 3.3 v, 10- 220-mhz, low jitter, 5 output zero delay buffer document number: 38-07759 revision ecn orig. of change submission date description of change ** 349620 rgl see ecn new datasheet *a 401073 rgl see ecn updated delay vs. load graph with standard drive data added phase-noise graph *b 413826 rgl see ecn minor change: typo ? changed from cy23ep05sxc-t to cy23ep05sxc-1t *c 3273677 cxq 06/07/2011 1) added typical column to the operating conditions table. included 3.3 v and 2.5 v typical specs for the two v dd rows. 2) all bw, r out , and theta j a specs are moved to typical column with only dashes left in the min and max columns. removed the ?(typical)? note from the description cells for these specs. 3) all other specs just have a dash for the new typical column cells. 4) changed i il spec in 3.3-v dc electrical specifications and 2.5-v dc electrical specifications tables from +/? 10 a max to ?10 a min and 10 a max. 5) added typical column to the dc elec trical specifications tables. typical column is all kept dashes except for th e first row v dd (3.3 v or 2.5 v respec- tively). 6) changed t 7 spec from +/? 150 ps max to ?150 ps min and 150 ps max (same for the 300 ps spec). 7) updated package drawing to latest revision. 8) added ordering code definitions, acronyms, units sections. [+] feedback
document #: 38-07759 rev. *c revised june 7, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy23ep05 ? cypress semiconductor corporation, 2005-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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